The following descriptions and examples are given as background information only.
Integrated circuit semiconductor devices using CMOS technology inherently contain parasitic bipolar pnp and npn transistors in the structure of p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) devices. For example, in a structure of a n-well CMOS circuit, a parasitic pnp bipolar transistor may be formed when a source/drain region of a PMOS device acts as an emitter, the n-well of the PMOS device acts as a base, and a p-type doped substrate acts as the collector. In addition, a parasitic npn bipolar transistor may be formed when a source/drain region of the NMOS device acts as an emitter, a substrate tie of the NMOS device acts as a base, and the n-well of the PMOS device acts as the collector. Since the parasitic bipolar transistors are connected through the n-well of the PMOS device (serving as the collector of the npn bipolar transistor and the base of the pnp bipolar transistor) and through p-type doped substrate (serving as the collector of the pnp bipolar transistor and the base of the npn bipolar transistor), the transistors interact electrically to form a pnpn diode structure equating to a silicon controlled rectifier (SCR).
A disadvantage of forming an SCR within a CMOS circuit is that it allows a low-resistance path between power supply buses to form, which in turn allows high amounts of current to flow through the circuit. In some cases, the current through the circuit can be amplified to a level at which one or more memory cells are in a state where they cannot be switched. In particular, internal voltages across the anode and cathode of an SCR which exceed a breakover or trigger voltage can cause junctions within the bipolar transistors of the circuit to become forward-biased. As a result, the SCR enters into a low impedance state with the possibility of a resultant high current. The low impedance state can be maintained indefinitely if a minimum holding current can be supplied to the circuit. As a consequence, the memory cells of the circuit may be restricted from switching and may lose their data. The SCR, in such a state, is commonly referred to as being latched up and, thus, the phenomenon of inducing a circuit into such a state is commonly referred to as “latch up.”
As device dimensions continue to decrease and device density increases, the latch up phenomenon becomes more prevalent. In particular, the closer NMOS and PMOS devices are fabricated relative to each other, the breakover voltage needed to forward-bias junctions within pnpn diode structures created therefrom as well as the minimum holding current needed to maintain a circuit in such a state decrease. As such, various techniques for controlling latch up in CMOS circuits have been proposed and are used in the microelectronics fabrication industry. For example, one method for controlling latch up in CMOS circuits involves incorporating well and/or substrate taps within a circuit to respectively reduce well and substrate resistances. In order to realize the benefit of such a technique, the taps are generally fabricated within each cell of a memory array. As a consequence, cell size is undesirably increased and the objective to increase memory cell density is hindered. In addition, the fabrication of contacts is sensitive to processing parameters of the circuit, such as mask alignment, for example.
Another technique used in the microelectronics industry for controlling latch up in CMOS circuits includes the formation of low resistance well regions having a varied doping profile within the substrate of the circuit. Such a technique is used to reduce the current-gain product of the parasitic bipolar transistors of the CMOS circuit and retard minority carrier injection into active junctions of the device. The formation of low resistance well regions, however, induces higher junction capacitance, which may undesirably increase the threshold voltage at which devices operate. Higher threshold voltages lead to decreased circuit speeds, which is contrary to the industry objective to increase processing speeds within circuits. Moreover, the formation of low resistance well regions does not completely eliminate the formation of latch up. In addition, well region fabrication is sensitive to processing parameters of the circuit, such as mask alignment and processing temperatures, for example. In particular, the placement of well regions within a circuit is directly dependent on the correct alignment of masks with the substrate. Misplacement of well regions may adversely affect the functionality of the device and, in some cases, cause the device to malfunction. In addition, the diffusion of dopants both vertically and horizontally can vary with the temperature, affecting the efficacy of low resistance wells. Furthermore, the activation of dopants to form well regions involves a thermal process, which is an additional restraint for the overall thermal budget of the device.
It would, therefore, be advantageous to develop other manners in which to prevent latch up in CMOS circuits. In particular, it would be beneficial to develop techniques for preventing latch up which do not increase memory cell size, are less sensitive to process variations and do not affect the functionality of the CMOS circuits.
While the invention may include various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.